Solid state drives, or SSDs, are mass storage devices that use flash memory for bulk memory storage rather than the rotating magnetic disks used in traditional hard disk drives (HDDs) and are typically intended as a drop-in replacement for HDDs, meaning that the SSD is pin- and protocol-compatible with the HDD that it replaces. SSDs typically have faster access time and use less power than a comparable HDD, but usually cost substantially more than a comparable HDD. It is expected that SSDs will widely replace HDDs as the cost of SSDs continues to go down.
SSDs typically include a cache memory for temporarily storing data being read from or written to the SSD. Conventional SSD designs use SRAM for the level one (L1) cache, NAND or NOR flash memory for the level two (L2) cache, and NAND flash memory for the mass data storage (also called “bulk data storage” or “bulk storage”.) SDRAM is also used to store a flash transition list's (FTL's) metadata. The L1 cache can be part of SRAM, which can be on chip. The L1 cache can also be part of DRAM, which can be part of the storage device address space and solely addressable by the storage device. Though SRAM or DRAM improves the performance, neither technology is favorable to a low end/low cost SSD, as using SRAM or DRAM increases die size, cost of materials and power consumption.
There are disadvantages associated with these conventional SSD designs, however. Although the SRAM used for the L1 cache is fast, the memory density of SRAM is quite low compared to flash memory, and so the memory capacity of the L1 cache is relatively small. It is possible to increase the L1 cache capacity by increasing the amount of SRAM on the SSD, but this leads to increased die size and cost. As SSDs become commodity items, it is important to keep the size of the silicon die down, and so increasing the amount of SRAM on the SSD (referred to as “on-board SRAM”) is disfavored.
The flash memory typically used for the L2 cache has a high memory density relative to the die size, also has disadvantages. NOR flash is true random access memory, but has a lower memory density relative to NAND flash. NAND flash has a higher memory density relative to NOR flash, but must be accessed a page at a time, which necessitates the use of additional hardware, called the flash translation layer, or FTL, to make it appear as if the NAND flash supports true random access.
The use of an NAND flash for the L2 cache, however, imposes additional costs and constraints. Because flash is erasable only in large chunks, called pages—a common page size is 4096 bytes—modifying a single byte or word of NAND flash in actuality requires modification of an entire page at a time. Since flash memories degrade over time proportional to the number of program/erase cycles performed, the illusion of random access provided by the FTL has the undesired side effect of reducing the operating life flash memory.
Thus, the use of on-board flash as cache memory is less desirable than the use of RAM, and the use of SRAM as cache memory is limited by the physical size constraints of the on-board SRAM memory that would be required. Therefore, what is desired is an SSD that provides the advantages of a large RAM cache but without the disadvantages of either on-board flash or on-board SRAM. In addition, it is desirable to have an SSD architecture that can be configured for use for either high-end (high cost, high performance) and low-end (low cost, low power consumption) markets.
Accordingly, in light of these disadvantages associated with conventional SSD architectures, solid state drive caching across a host bus is desirable. When performing solid state drive caching across a host bus, a portion of host DRAM is used to cache data, such as FTL tables, for the SSD. Allowing host DRAM to be used as a cache by the SSD makes SSD operations more efficient and reduces the requirement for on-board DRAM in the SSD. However, if host DRAM is being used by the SSD, that portion of the DRAM is not available to the host and may adversely impact the performance of the host. The portion of host DRAM used for caching SSD data is referred to interchangeably herein as the host cache or host memory buffer. Because the host memory buffer is a shared resource between the SSD and the host, there exists a need for allocating the appropriate amount of DRAM for the host memory buffer that balances the needs of the SSD and the host and does not adversely affect the user experience. Accordingly, there exists a need for methods, systems, and computer readable media for providing a flexible host memory buffer.